Conventional die-level packaged microelectronic devices typically include a microelectronic die, an interposer substrate or lead frame attached to the die, and a moulded casing around the die. The die generally includes an integrated circuit coupled to a plurality of bond-pads. The bond-pads are typically coupled to contacts on the interposer substrate or lead frame, and serve as external electrical contacts through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to contacts, interposer substrates can also include ball-pads coupled to the contacts by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages that have lower profiles and higher pin counts than conventional packages using lead frames.
One process for making a packaged microelectronic device with a ball-grid array includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding bond-pads on the dies to contacts on the interposer substrate, and (e) encapsulating the dies with a suitable moulding compound. Packaged microelectronic devices made in the foregoing manner are often used in cellphones, pagers, personal digital assistants, computers, and other electronic products. As the demand for these products grows, there is a continuing drive to increase the performance of packaged microelectronic devices while at the same time reducing the height and surface area or “footprint” of such devices on printed circuit boards. Reducing the size of microelectronic devices, however, becomes more difficult as the performance increases because higher performance typically requires more integrated circuitry and bond-pads. In addition, increasing circuit density can lead to noise during high-speed signal transmission.
FIG. 1 is a schematic cross-sectional view of a packaged microelectronic device 100 configured in accordance with the prior art. The packaged microelectronic device 100 includes a die 130 bonded to an interposer substrate 120 in a conventional “board on chip” arrangement. The interposer substrate 120 includes a sheet of non-conductive material 123 (e.g., BT resin, FR4, etc.) having a first side 121, an opposing second side 122, and a slot 125 extending therethrough. Conductive traces 126 (identified individually as a first conductive trace 126a and a second conductive trace 126b) are formed on the first side 121 of the non-conductive material 123 on opposite sides of the slot 125. Each of the conductive traces 126 extends between a contact 127 and a corresponding ball-pad 128. Solder balls 129 can be deposited on the ball-pads 128 to form part of a ball-grid array.
The die 130 includes an integrated circuit 132 electrically coupled to a series of bond-pads 134 (only one of the bond-pads 134 is shown in FIG. 1). The integrated circuit 132 is electrically coupled to the ball-grid array by individual wire-bonds 136 that extend from the bond-pads 134 to the contacts 127. After the wire-bonds 136 have been attached, the die 130 and the adjacent portion of the substrate 120 can be encased in a suitable mold compound 140.
As the speed of the packaged microelectronic device 100 increases and the size becomes smaller, the first side 121 of the non-conductive material 123 becomes very congested with conductive traces. The congestion limits the ability to match input and output trace lengths to reduce signal transmission problems. In addition, the close proximity of signal traces to ground and power planes or ground and power traces can cause signal noise due to a phenomenon known as ground/power bounce.
FIG. 2 is a schematic cross-sectional view of a packaged microelectronic device 200 having conductive traces 226 on both sides of a substrate 220. Specifically, the substrate 220 includes a first conductive trace 226a on a first side 221 of a non-conductive material 223, and a second conductive trace 226b on a second side 222 of the non-conductive material 223. A portion of a plated via 250 extends through the non-conductive material 223 to electrically couple the second conductive trace 226b to a contact 227 on the first side 221.
Although moving the second conductive trace 226b to the second side 222 of the substrate 220 does reduce the trace count on the first side 221, the plated via 250 still adds to the congestion on the first side 221 and can cause trace routing constraints. A further shortcoming of this configuration is that the plated via 250 increases the length of the inductance loop when the second conductive trace 226b is used for power or ground purposes. Increasing the length of the inductance loop can cause additional noise during signal transmission.